git.libre-soc.org Git - gem5.git/commit

author	Yasuko Eckert <yasuko.eckert@amd.com>
	Tue, 15 Oct 2013 18:22:44 +0000 (14:22 -0400)
committer	Yasuko Eckert <yasuko.eckert@amd.com>
	Tue, 15 Oct 2013 18:22:44 +0000 (14:22 -0400)
commit	2c293823aa7cb6d2cac4c0ff35e2023ff132a8f2
tree	040fdd5bad814d7cb7ee40934974d2b38b28d67a	tree
parent	552622184752dc798bc81f9b0b395db68aee9511	commit \| diff

cpu: add a condition-code register class

Add a third register class for condition codes,
in parallel with the integer and FP classes.
No ISAs use the CC class at this point though.

57 files changed:

src/arch/SConscript		diff \| blob \| history
src/arch/alpha/isa.hh		diff \| blob \| history
src/arch/alpha/registers.hh		diff \| blob \| history
src/arch/alpha/utility.cc		diff \| blob \| history
src/arch/arm/insts/static_inst.cc		diff \| blob \| history
src/arch/arm/isa.hh		diff \| blob \| history
src/arch/arm/registers.hh		diff \| blob \| history
src/arch/arm/utility.cc		diff \| blob \| history
src/arch/isa_parser.py		diff \| blob \| history
src/arch/mips/isa.hh		diff \| blob \| history
src/arch/mips/registers.hh		diff \| blob \| history
src/arch/null/registers.hh		diff \| blob \| history
src/arch/power/insts/static_inst.cc		diff \| blob \| history
src/arch/power/isa.hh		diff \| blob \| history
src/arch/power/registers.hh		diff \| blob \| history
src/arch/power/utility.cc		diff \| blob \| history
src/arch/sparc/isa.hh		diff \| blob \| history
src/arch/sparc/registers.hh		diff \| blob \| history
src/arch/sparc/utility.cc		diff \| blob \| history
src/arch/x86/insts/static_inst.cc		diff \| blob \| history
src/arch/x86/isa.hh		diff \| blob \| history
src/arch/x86/registers.hh		diff \| blob \| history
src/arch/x86/utility.cc		diff \| blob \| history
src/cpu/base_dyn_inst.hh		diff \| blob \| history
src/cpu/checker/cpu.hh		diff \| blob \| history
src/cpu/checker/cpu_impl.hh		diff \| blob \| history
src/cpu/checker/thread_context.hh		diff \| blob \| history
src/cpu/inorder/cpu.cc		diff \| blob \| history
src/cpu/inorder/cpu.hh		diff \| blob \| history
src/cpu/inorder/inorder_dyn_inst.cc		diff \| blob \| history
src/cpu/inorder/inorder_dyn_inst.hh		diff \| blob \| history
src/cpu/inorder/thread_context.cc		diff \| blob \| history
src/cpu/inorder/thread_context.hh		diff \| blob \| history
src/cpu/o3/O3CPU.py		diff \| blob \| history
src/cpu/o3/cpu.cc		diff \| blob \| history
src/cpu/o3/cpu.hh		diff \| blob \| history
src/cpu/o3/dyn_inst.hh		diff \| blob \| history
src/cpu/o3/free_list.cc		diff \| blob \| history
src/cpu/o3/free_list.hh		diff \| blob \| history
src/cpu/o3/inst_queue.hh		diff \| blob \| history
src/cpu/o3/inst_queue_impl.hh		diff \| blob \| history
src/cpu/o3/regfile.cc		diff \| blob \| history
src/cpu/o3/regfile.hh		diff \| blob \| history
src/cpu/o3/rename_impl.hh		diff \| blob \| history
src/cpu/o3/rename_map.cc		diff \| blob \| history
src/cpu/o3/rename_map.hh		diff \| blob \| history
src/cpu/o3/thread_context.hh		diff \| blob \| history
src/cpu/o3/thread_context_impl.hh		diff \| blob \| history
src/cpu/ozone/cpu_impl.hh		diff \| blob \| history
src/cpu/reg_class.cc		diff \| blob \| history
src/cpu/reg_class.hh		diff \| blob \| history
src/cpu/simple/base.cc		diff \| blob \| history
src/cpu/simple/base.hh		diff \| blob \| history
src/cpu/simple_thread.hh		diff \| blob \| history
src/cpu/static_inst.hh		diff \| blob \| history
src/cpu/thread_context.cc		diff \| blob \| history
src/cpu/thread_context.hh		diff \| blob \| history

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