Merge pull request #1778 from rswarbrick/sv-defines
authorN. Engelhardt <nak@symbioticeda.com>
Mon, 30 Mar 2020 11:51:12 +0000 (13:51 +0200)
committerGitHub <noreply@github.com>
Mon, 30 Mar 2020 11:51:12 +0000 (13:51 +0200)
commit2c847e7efec5e940331a94580fad99375ce73c6f
treec87b514d072beb687287ae0432e57964bf0999b9
parent1dbc70172830c57cda22e4bc82d2db57a2067203
parent044ca9dde409e3c91542fe95513d6641110f8462
Merge pull request #1778 from rswarbrick/sv-defines

Add support for SystemVerilog-style `define to Verilog frontend