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(parent: b3d9bf6) | patch
hdl.ir: lower domains before resolving hierarchy conflicts.
authorwhitequark <cz@m-labs.hk>
Thu, 7 Nov 2019 08:20:27 +0000 (08:20 +0000)
committerwhitequark <cz@m-labs.hk>
Thu, 7 Nov 2019 08:20:27 +0000 (08:20 +0000)
commit2c88b3f24cdcbc5dc108817e511a81ccefe55413
tree16f8684f5cea96ea2f9ea07ed9b6f00030eb9174tree
parentb3d9bf6da7f50f8321ccedc033b17aacce2b7172commit | diff
hdl.ir: lower domains before resolving hierarchy conflicts.

Otherwise, two subfragments with the same local clock domain would
not be able to drive its clock or reset signals. This can be easily
hit if using two ResetSynchronizers in one module.

Fixes #265.
nmigen/hdl/ir.py diff | blob | history
nmigen/test/test_hdl_ir.py diff | blob | history