add first (correctly-working) ctr-mode sv.bc test
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 22 Sep 2022 23:47:26 +0000 (00:47 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 22 Sep 2022 23:49:58 +0000 (00:49 +0100)
commit2cb88ba7019ea80498060621155179020ca543d5
tree97355e48218a27d877efcdfe8e026263e97f918e
parentbc1c2b6287b21be0c118fe5641dadc487b56151f
add first (correctly-working) ctr-mode sv.bc test
openpower/isa/svbranch.mdwn
src/openpower/decoder/isa/caller.py
src/openpower/decoder/isa/test_caller_svp64_bc.py