Fix ignoring of simulation timings so that invalid module parameters cause syntax...
authorClifford Wolf <clifford@clifford.at>
Mon, 25 Sep 2017 23:52:59 +0000 (01:52 +0200)
committerClifford Wolf <clifford@clifford.at>
Mon, 25 Sep 2017 23:52:59 +0000 (01:52 +0200)
commit2cc09161ffd774430293dfd18e307e75bea73c5e
tree9c018ea7954daddaaa8e6cc89502ed522f3a30a9
parent143c0abd33ed76b2a7e38dbbac1767e6f7edd68f
Fix ignoring of simulation timings so that invalid module parameters cause syntax errors
frontends/verilog/verilog_lexer.l
frontends/verilog/verilog_parser.y