i965/fs: Implement lowering of logical texturing opcodes on Gen4.
authorFrancisco Jerez <currojerez@riseup.net>
Sat, 18 Jul 2015 14:09:37 +0000 (17:09 +0300)
committerFrancisco Jerez <currojerez@riseup.net>
Wed, 29 Jul 2015 11:12:48 +0000 (14:12 +0300)
commit2cd466f6c3192015ea1794afc57eb453d7f13818
tree42496a35445542a4a43231003edb1742f70c7f48
parent501134b9fe02633ca0cdda66a9b670ae38e791f7
i965/fs: Implement lowering of logical texturing opcodes on Gen4.

Unlike its Gen5 and Gen7 counterparts this patch isn't a plain
refactor of the previous Gen4 texturing code, it's more of a rewrite
largely based on emit_texture_gen4_simd16().  The reason is that on
the one hand the original emit_texture_gen4() code didn't seem easily
fixable to be SIMD width-invariant and had plenty of clutter to
support SIMD-width workarounds which are no longer required.  On the
other hand emit_texture_gen4_simd16() was missing a number of
SIMD8-only opcodes.  This should generalize both and roughly match
their current behaviour where there is overlap.

Incidentally this will fix the following piglits on Gen4:

    arb_shader_texture_lod.execution.arb_shader_texture_lod-texgrad
    arb_shader_texture_lod.execution.tex-miplevel-selection *gradarb 2d
    arb_shader_texture_lod.execution.tex-miplevel-selection *gradarb 3d
    arb_shader_texture_lod.execution.tex-miplevel-selection *projgradarb 2d
    arb_shader_texture_lod.execution.tex-miplevel-selection *projgradarb 2d_projvec4
    arb_shader_texture_lod.execution.tex-miplevel-selection *projgradarb 3d

Acked-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
src/mesa/drivers/dri/i965/brw_fs.cpp