arch,cpu: Enforce using accessors to get at src/destRegIdx.
authorGabe Black <gabe.black@gmail.com>
Sun, 1 Nov 2020 08:53:03 +0000 (01:53 -0700)
committerGabe Black <gabe.black@gmail.com>
Fri, 6 Nov 2020 00:57:38 +0000 (00:57 +0000)
commit2cfc24b8dc27acc0ef2ac421b79f839c0354fefd
treef145340d1445e93499ee97ec4a11882fc78d72c7
parenta82ea84244b47dd429560eb6013250ed90dcaa5c
arch,cpu: Enforce using accessors to get at src/destRegIdx.

There were accessors for reading these indexes, but they were not
consistently used. This change makes them private to StaticInst, and
changes places that were accessing them directly to instead use the
accessors. New accessors are added for code generated by the ISA parser
and some ARM code to set the indexes without accessing them directly.

By forcing these values to be behind accessors, it will be much simpler
to change how those values are stored and retrieved.

Change-Id: Icca80023d7f89e29504fac6b194881f88aedeec2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36875
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
43 files changed:
src/arch/arm/insts/tme64.cc
src/arch/arm/isa/templates/basic.isa
src/arch/arm/isa/templates/branch.isa
src/arch/arm/isa/templates/macromem.isa
src/arch/arm/isa/templates/mem.isa
src/arch/arm/isa/templates/mem64.isa
src/arch/arm/isa/templates/misc.isa
src/arch/arm/isa/templates/mult.isa
src/arch/arm/isa/templates/neon.isa
src/arch/arm/isa/templates/pred.isa
src/arch/arm/isa/templates/semihost.isa
src/arch/arm/isa/templates/sve_mem.isa
src/arch/arm/isa/templates/vfp.isa
src/arch/isa_parser/operand_types.py
src/arch/mips/isa/base.isa
src/arch/mips/isa/formats/branch.isa
src/arch/mips/isa/formats/fp.isa
src/arch/mips/isa/formats/int.isa
src/arch/power/insts/branch.cc
src/arch/power/insts/floating.cc
src/arch/power/insts/integer.cc
src/arch/power/insts/mem.cc
src/arch/power/insts/misc.cc
src/arch/riscv/insts/amo.cc
src/arch/riscv/insts/compressed.cc
src/arch/riscv/insts/mem.cc
src/arch/riscv/insts/standard.cc
src/arch/riscv/isa/formats/compressed.isa
src/arch/riscv/isa/formats/standard.isa
src/arch/sparc/insts/blockmem.cc
src/arch/sparc/insts/branch.cc
src/arch/sparc/insts/integer.cc
src/arch/sparc/insts/mem.cc
src/arch/sparc/insts/priv.cc
src/arch/sparc/insts/static_inst.cc
src/arch/sparc/insts/static_inst.hh
src/arch/sparc/insts/trap.cc
src/arch/x86/insts/static_inst.cc
src/arch/x86/insts/static_inst.hh
src/arch/x86/isa/formats/cpuid.isa
src/arch/x86/isa/formats/monitor_mwait.isa
src/arch/x86/isa/formats/syscall.isa
src/cpu/static_inst.hh