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(parent: 83a3212) | patch
sigh, update setvl tests, to spec, and ISACaller
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 26 Aug 2022 15:02:18 +0000 (16:02 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 26 Aug 2022 15:02:18 +0000 (16:02 +0100)
commit2d1e5215b1089fa7e2f1bfba53f6d012ba6dd927
treef8081eae27144d73d27672b3eae51c4e5102ba8ftree
parent83a3212c234c413e8e5b670a18840f0a8a7f7190commit | diff
sigh, update setvl tests, to spec, and ISACaller
https://libre-soc.org/openpower/sv/setvl/
see Rc=1 section: it is possible to have Rc=1, RT=0, RA!=0 which
means "set VL but do not set RT" which *still* requires that Rc=1
be updated - not from RT but from VL
openpower/isa/simplev.mdwn diff | blob | history
src/openpower/decoder/isa/caller.py diff | blob | history
src/openpower/decoder/isa/test_caller_setvl.py diff | blob | history