Enable direct movement between gpr and mask registers in pass_reload.
authorliuhongt <hongtao.liu@intel.com>
Thu, 6 Aug 2020 05:48:38 +0000 (13:48 +0800)
committerliuhongt <hongtao.liu@intel.com>
Fri, 21 Aug 2020 04:48:31 +0000 (12:48 +0800)
commit2d2bc36c4440c126decee5a8379c158d9012adfc
tree3a5799bf1bcb9418d74e9b9fac6939a07ee62d2a
parent00cb3494cab397b5655ab42fd69310883c12137c
Enable direct movement between gpr and mask registers in pass_reload.

Changelog
gcc/
* config/i386/i386.c (inline_secondary_memory_needed):
No memory is needed between mask regs and gpr.
(ix86_hard_regno_mode_ok): Add condition TARGET_AVX512F for
mask regno.
* config/i386/i386.h (enum reg_class): Add INT_MASK_REGS.
(REG_CLASS_NAMES): Ditto.
(REG_CLASS_CONTENTS): Ditto.
* config/i386/i386.md: Exclude mask register in
define_peephole2 which is avaiable only for gpr.

gcc/testsuite/
* gcc.target/i386/spill_to_mask-1.c: New tests.
* gcc.target/i386/spill_to_mask-2.c: New tests.
* gcc.target/i386/spill_to_mask-3.c: New tests.
* gcc.target/i386/spill_to_mask-4.c: New tests.
gcc/config/i386/i386.c
gcc/config/i386/i386.h
gcc/config/i386/i386.md
gcc/testsuite/gcc.target/i386/spill_to_mask-1.c [new file with mode: 0644]
gcc/testsuite/gcc.target/i386/spill_to_mask-2.c [new file with mode: 0644]
gcc/testsuite/gcc.target/i386/spill_to_mask-3.c [new file with mode: 0644]
gcc/testsuite/gcc.target/i386/spill_to_mask-4.c [new file with mode: 0644]