Also allow "module foobar(input foo, output bar, ...);" syntax
authorClifford Wolf <clifford@clifford.at>
Thu, 7 Aug 2014 14:41:27 +0000 (16:41 +0200)
committerClifford Wolf <clifford@clifford.at>
Thu, 7 Aug 2014 14:41:27 +0000 (16:41 +0200)
commit2dc33337346ea53a654af3d80bdf056c7ccfa43c
tree85bb47c1f10a6a82b79472ace19da4258ff5f295
parent312ee00c9e279a91f336acef26dd064c25f42ed5
Also allow "module foobar(input foo, output bar, ...);" syntax
frontends/verilog/parser.y