hdl.cd: add negedge clock domains.
authorwhitequark <whitequark@whitequark.org>
Sat, 31 Aug 2019 22:05:48 +0000 (22:05 +0000)
committerwhitequark <whitequark@whitequark.org>
Sat, 31 Aug 2019 22:05:48 +0000 (22:05 +0000)
commit2e206220462c67aa6ae97f7515a2191440fd61b3
treed72d153b57c0eb02e11f5f59b069ef1d0bdee8ab
parentc4e8ac734f3f3eaf1438786362e4d55fdbc3d539
hdl.cd: add negedge clock domains.

Fixes #185.
nmigen/back/pysim.py
nmigen/back/rtlil.py
nmigen/hdl/cd.py
nmigen/test/test_hdl_cd.py