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(parent: b523ecf) | patch
verilog: ignore '&&&' when not in -specify mode
authorEddie Hung <eddie@fpgeh.com>
Thu, 13 Feb 2020 21:06:13 +0000 (13:06 -0800)
committerEddie Hung <eddie@fpgeh.com>
Thu, 13 Feb 2020 21:06:13 +0000 (13:06 -0800)
commit2e51dc1856aae456e15cafd484997bfbd102175e
treee446b57a8d99be177068c96e15e4f9753ec8b402tree
parentb523ecf2f45f80488412781ba9a3455a71d64d62commit | diff
verilog: ignore '&&&' when not in -specify mode
frontends/verilog/verilog_lexer.l diff | blob | history
frontends/verilog/verilog_parser.y diff | blob | history
tests/various/specify.v diff | blob | history