mem: Rename Packet::checkFunctional to trySatisfyFunctional
authorRobert Kovacsics <rmk35@cl.cam.ac.uk>
Thu, 19 Jul 2018 17:56:06 +0000 (18:56 +0100)
committerKovacsics Róbert <kovirobi@gmail.com>
Mon, 23 Jul 2018 11:57:50 +0000 (11:57 +0000)
commit2f17062dd9a465943b57723f72f89ec66a0db664
treeb1b017079a912021b892e159572e3d8055181b66
parent4158138d1f0ef14b7be2f55382836821b7ac09d5
mem: Rename Packet::checkFunctional to trySatisfyFunctional

Packet::checkFunctional also wrote data to/from the packet depending
on if it was read/write, respectively, which the 'check' in the name
would suggest otherwise. This renames it to doFunctional, which is
more suggestive. It also renames any function called checkFunctional
which calls Packet::checkFunctional. These are

- Bridge::BridgeMasterPort::checkFunctional
  - calls Packet::checkFunctional
- MSHR::checkFunctional
  - calls Packet::checkFunctional
- MSHR::TargetList::checkFunctional
  - calls Packet::checkFunctional
- Queue<>::checkFunctional
  (of src/mem/cache/queue.hh, not src/cpu/minor/buffers.h)
  - Instantiated with Queue<WriteQueueEntry> and Queue<MSHR>
- WriteQueueEntry
  - calls Packet::checkFunctional
- WriteQueueEntry::TargetList
  - calls Packet::checkFunctional
- MemDelay::checkFunctional
  - calls QueuedSlavePort/QueuedMasterPort::checkFunctional
- Packet::checkFunctional
- PacketQueue::checkFunctional
  - calls Packet::checkFunctional
- QueuedSlavePort::checkFunctional
  - calls PacketQueue::doFunctional
- QueuedMasterPort::checkFunctional
  - calls PacketQueue::doFunctional
- SerialLink::SerialLinkMasterPort::checkFunctional
  - calls Packet::doFunctional

Change-Id: Ieca2579c020c329040da053ba8e25820801b62c5
Reviewed-on: https://gem5-review.googlesource.com/11810
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
24 files changed:
src/mem/bridge.cc
src/mem/bridge.hh
src/mem/cache/base.cc
src/mem/cache/mshr.cc
src/mem/cache/mshr.hh
src/mem/cache/queue.hh
src/mem/cache/write_queue_entry.cc
src/mem/cache/write_queue_entry.hh
src/mem/coherent_xbar.cc
src/mem/dram_ctrl.cc
src/mem/dramsim2.cc
src/mem/mem_delay.cc
src/mem/mem_delay.hh
src/mem/noncoherent_xbar.cc
src/mem/packet.cc
src/mem/packet.hh
src/mem/packet_queue.cc
src/mem/packet_queue.hh
src/mem/qport.hh
src/mem/ruby/slicc_interface/AbstractController.cc
src/mem/serial_link.cc
src/mem/serial_link.hh
src/mem/simple_mem.cc
src/mem/tport.cc