git.libre-soc.org Git - gem5.git/commit

author	Nilay Vaish <nilay@cs.wisc.edu>
	Wed, 19 Aug 2015 15:02:01 +0000 (10:02 -0500)
committer	Nilay Vaish <nilay@cs.wisc.edu>
	Wed, 19 Aug 2015 15:02:01 +0000 (10:02 -0500)
commit	2f44dada688ace9c24f085a8422b3054c3edb72e
tree	372bb043430552b0f4424eaa5571933883fcaaae	tree
parent	2d9f3f8582e2de60850852c803a8c8ba0d6b91b5	commit \| diff

ruby: reverts to changeset: bf82f1f7b040

81 files changed:

configs/ruby/Ruby.py		diff \| blob \| history
src/cpu/testers/directedtest/RubyDirectedTester.hh		diff \| blob \| history
src/cpu/testers/rubytest/RubyTester.hh		diff \| blob \| history
src/mem/protocol/MESI_Three_Level-L0cache.sm		diff \| blob \| history
src/mem/protocol/MESI_Three_Level-L1cache.sm		diff \| blob \| history
src/mem/protocol/MESI_Two_Level-L1cache.sm		diff \| blob \| history
src/mem/protocol/MESI_Two_Level-L2cache.sm		diff \| blob \| history
src/mem/protocol/MESI_Two_Level-dir.sm		diff \| blob \| history
src/mem/protocol/MI_example-cache.sm		diff \| blob \| history
src/mem/protocol/MI_example-dir.sm		diff \| blob \| history
src/mem/protocol/MOESI_CMP_directory-L1cache.sm		diff \| blob \| history
src/mem/protocol/MOESI_CMP_directory-L2cache.sm		diff \| blob \| history
src/mem/protocol/MOESI_CMP_directory-dir.sm		diff \| blob \| history
src/mem/protocol/MOESI_CMP_directory-dma.sm		diff \| blob \| history
src/mem/protocol/MOESI_CMP_token-L1cache.sm		diff \| blob \| history
src/mem/protocol/MOESI_CMP_token-dir.sm		diff \| blob \| history
src/mem/protocol/MOESI_hammer-cache.sm		diff \| blob \| history
src/mem/protocol/MOESI_hammer-dir.sm		diff \| blob \| history
src/mem/protocol/RubySlicc_Types.sm		diff \| blob \| history
src/mem/ruby/common/DataBlock.hh		diff \| blob \| history
src/mem/ruby/common/Histogram.cc		diff \| blob \| history
src/mem/ruby/common/Histogram.hh		diff \| blob \| history
src/mem/ruby/common/SubBlock.cc		diff \| blob \| history
src/mem/ruby/common/SubBlock.hh		diff \| blob \| history
src/mem/ruby/common/TypeDefines.hh		diff \| blob \| history
src/mem/ruby/filters/H3BloomFilter.cc		diff \| blob \| history
src/mem/ruby/filters/H3BloomFilter.hh		diff \| blob \| history
src/mem/ruby/filters/MultiBitSelBloomFilter.cc		diff \| blob \| history
src/mem/ruby/filters/MultiBitSelBloomFilter.hh		diff \| blob \| history
src/mem/ruby/network/MessageBuffer.cc		diff \| blob \| history
src/mem/ruby/network/MessageBuffer.hh		diff \| blob \| history
src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc		diff \| blob \| history
src/mem/ruby/network/garnet/flexible-pipeline/flit.cc		diff \| blob \| history
src/mem/ruby/network/garnet/flexible-pipeline/flit.hh		diff \| blob \| history
src/mem/ruby/network/simple/PerfectSwitch.cc		diff \| blob \| history
src/mem/ruby/network/simple/PerfectSwitch.hh		diff \| blob \| history
src/mem/ruby/network/simple/SimpleNetwork.cc		diff \| blob \| history
src/mem/ruby/network/simple/SimpleNetwork.hh		diff \| blob \| history
src/mem/ruby/network/simple/Switch.cc		diff \| blob \| history
src/mem/ruby/network/simple/Throttle.cc		diff \| blob \| history
src/mem/ruby/network/simple/Throttle.hh		diff \| blob \| history
src/mem/ruby/profiler/AccessTraceForAddress.hh		diff \| blob \| history
src/mem/ruby/profiler/AddressProfiler.cc		diff \| blob \| history
src/mem/ruby/profiler/AddressProfiler.hh		diff \| blob \| history
src/mem/ruby/profiler/Profiler.cc		diff \| blob \| history
src/mem/ruby/profiler/Profiler.hh		diff \| blob \| history
src/mem/ruby/profiler/StoreTrace.cc		diff \| blob \| history
src/mem/ruby/profiler/StoreTrace.hh		diff \| blob \| history
src/mem/ruby/slicc_interface/AbstractCacheEntry.cc		diff \| blob \| history
src/mem/ruby/slicc_interface/AbstractCacheEntry.hh		diff \| blob \| history
src/mem/ruby/slicc_interface/AbstractController.hh		diff \| blob \| history
src/mem/ruby/structures/AbstractReplacementPolicy.cc		diff \| blob \| history
src/mem/ruby/structures/AbstractReplacementPolicy.hh		diff \| blob \| history
src/mem/ruby/structures/BankedArray.cc		diff \| blob \| history
src/mem/ruby/structures/BankedArray.hh		diff \| blob \| history
src/mem/ruby/structures/CacheMemory.cc		diff \| blob \| history
src/mem/ruby/structures/CacheMemory.hh		diff \| blob \| history
src/mem/ruby/structures/DirectoryMemory.cc		diff \| blob \| history
src/mem/ruby/structures/DirectoryMemory.hh		diff \| blob \| history
src/mem/ruby/structures/LRUPolicy.cc		diff \| blob \| history
src/mem/ruby/structures/LRUPolicy.hh		diff \| blob \| history
src/mem/ruby/structures/PseudoLRUPolicy.cc		diff \| blob \| history
src/mem/ruby/structures/PseudoLRUPolicy.hh		diff \| blob \| history
src/mem/ruby/structures/RubyMemoryControl.cc		diff \| blob \| history
src/mem/ruby/structures/RubyMemoryControl.hh		diff \| blob \| history
src/mem/ruby/system/CacheRecorder.cc		diff \| blob \| history
src/mem/ruby/system/CacheRecorder.hh		diff \| blob \| history
src/mem/ruby/system/RubySystem.py		diff \| blob \| history
src/mem/ruby/system/Sequencer.cc		diff \| blob \| history
src/mem/ruby/system/System.cc		diff \| blob \| history
src/mem/ruby/system/System.hh		diff \| blob \| history
src/mem/slicc/ast/EnumDeclAST.py		diff \| blob \| history
src/mem/slicc/ast/FormalParamAST.py		diff \| blob \| history
src/mem/slicc/ast/FuncCallExprAST.py		diff \| blob \| history
src/mem/slicc/ast/FuncDeclAST.py		diff \| blob \| history
src/mem/slicc/ast/InPortDeclAST.py		diff \| blob \| history
src/mem/slicc/ast/MethodCallExprAST.py		diff \| blob \| history
src/mem/slicc/ast/StateDeclAST.py		diff \| blob \| history
src/mem/slicc/parser.py		diff \| blob \| history
src/mem/slicc/symbols/Func.py		diff \| blob \| history
src/mem/slicc/symbols/StateMachine.py		diff \| blob \| history

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