Split SimpleCPU into two different models, AtomicSimpleCPU and
authorSteve Reinhardt <stever@eecs.umich.edu>
Tue, 16 May 2006 21:36:50 +0000 (17:36 -0400)
committerSteve Reinhardt <stever@eecs.umich.edu>
Tue, 16 May 2006 21:36:50 +0000 (17:36 -0400)
commit309e1d81939c44f6b31795be84868605e05b09ec
tree1f079bbcb38e79b3221e59cf03c43dd2bd174770
parent2db12b3d6cdcb840ef41dbe3e4a8db1821d7c4de
Split SimpleCPU into two different models, AtomicSimpleCPU and
TimingSimpleCPU, which use atomic and timing memory accesses
respectively.  Common code is factored into the BaseSimpleCPU class.
AtomicSimpleCPU includes an option (simulate_stalls) to add delays
based on the estimated latency reported by the atomic accesses.
Plain old "SimpleCPU" is gone; I have not updated all the config
files (just test/test.py).
Also fixes to get timing accesses working in new memory model and
to get split-phase memory instruction definitions working with
new memory model as well.

arch/alpha/isa/main.isa:
    Need to include packet_impl.h for functions that use Packet objects.
arch/alpha/isa/mem.isa:
    Change completeAcc() methods to take Packet object pointers.
    Also split out StoreCond template for completeAcc(), since
    that's the only one that needs write_result and we get an
    unused variable warning if we always have it in there.
build/SConstruct:
    Update list of recognized CPU model names.
configs/test/test.py:
    Change SimpleCPU to AtomicSimpleCPU.
cpu/SConscript:
    Define sources for new CPU models.
    Add split memory access methods to CPU model signatures.
cpu/cpu_models.py:
cpu/static_inst.hh:
    Define new CPU models.
cpu/simple/base.cc:
cpu/simple/base.hh:
    Factor out pieces specific to Atomic or Timing models.
mem/bus.cc:
    Bus needs to be able to route timing packets based on explicit dest
    so responses can get back to requester.  Set dest to Packet::Broadcast
    to indicate that dest should be derived from address.
    Also set packet src field based on port from which packet is sent.
mem/bus.hh:
    Set packet src field based on port from which packet is sent.
mem/packet.hh:
    Define Broadcast destination address to indicate that
    packet should be routed based on address.
mem/physical.cc:
    Set packet dest on response so packet is routed
    back to requester properly.
mem/port.cc:
    Flag blob packets as Broadcast.
python/m5/objects/PhysicalMemory.py:
    Change default latency to be 1 cycle.

--HG--
rename : cpu/simple/cpu.cc => cpu/simple/base.cc
rename : cpu/simple/cpu.hh => cpu/simple/base.hh
extra : convert_revision : e9646af6406a20c8c605087936dc4683375c2132
21 files changed:
arch/alpha/isa/main.isa
arch/alpha/isa/mem.isa
build/SConstruct
configs/test/test.py
cpu/SConscript
cpu/cpu_models.py
cpu/simple/atomic.cc [new file with mode: 0644]
cpu/simple/atomic.hh [new file with mode: 0644]
cpu/simple/base.cc [new file with mode: 0644]
cpu/simple/base.hh [new file with mode: 0644]
cpu/simple/cpu.cc [deleted file]
cpu/simple/cpu.hh [deleted file]
cpu/simple/timing.cc [new file with mode: 0644]
cpu/simple/timing.hh [new file with mode: 0644]
cpu/static_inst.hh
mem/bus.cc
mem/bus.hh
mem/packet.hh
mem/physical.cc
mem/port.cc
python/m5/objects/PhysicalMemory.py