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(parent: 7ed36a3) | patch
add sv.cmp (ffirst-5) decode/encode asm support
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 6 Oct 2022 11:43:00 +0000 (12:43 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 6 Oct 2022 11:43:00 +0000 (12:43 +0100)
commit3191ca25e16c50d0f37a6b072b21b7471514097f
tree1264b681ff498f6c526dc58e939aff3f56c90b6dtree
parent7ed36a315cfc267570e16ecf774460ae7f7a0365commit | diff
add sv.cmp (ffirst-5) decode/encode asm support
* sv/trans/svp64.py needed a totally different ffirst handling
* CROpFF5RM needs to derive from FFPRRc0BaseRM and PredicateWidthBaseRM
src/openpower/decoder/power_insn.py diff | blob | history
src/openpower/sv/trans/svp64.py diff | blob | history
src/openpower/sv/trans/test_pysvp64dis.py diff | blob | history