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(parent: b3d68d5) | patch
i965/gen6: Stencil/hiz needs an offset for LOD > 0
authorJordan Justen <jordan.l.justen@intel.com>
Wed, 28 May 2014 17:19:37 +0000 (10:19 -0700)
committerJordan Justen <jordan.l.justen@intel.com>
Sat, 16 Aug 2014 03:11:42 +0000 (20:11 -0700)
commit31e1beec899d36904ee7b9629400a523fbc42210
treeea2e5237cc97b1df8569bc35a333eea8c40ade00tree
parentb3d68d5a30ac6964aefff65846e28d20af16c345commit | diff
i965/gen6: Stencil/hiz needs an offset for LOD > 0

Since gen6 separate stencil & hiz only supports LOD0, we need to
program an offset to the LOD when emitting the separate stencil/hiz.

v3:
 * Use new array_layout enum

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
src/mesa/drivers/dri/i965/gen6_blorp.cpp diff | blob | history
src/mesa/drivers/dri/i965/gen6_depth_state.c diff | blob | history