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(parent: 314a6c7) | patch
fhdl/verilog: fix spurious clock/reset signals on multiple calls to convert()
authorSebastien Bourdeauducq <sebastien@milkymist.org>
Wed, 23 Jan 2013 14:13:06 +0000 (15:13 +0100)
committerSebastien Bourdeauducq <sebastien@milkymist.org>
Wed, 23 Jan 2013 14:13:06 +0000 (15:13 +0100)
commit3201554f7646e8cbd007124104ee5198a1dbb83d
tree346aa09d36da5a50f6045440c5614154e66e65e9tree
parent314a6c774380a9d2f5c77f24fd3589728c8704f4commit | diff
fhdl/verilog: fix spurious clock/reset signals on multiple calls to convert()
migen/fhdl/verilog.py diff | blob | history