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(parent: 48d4ee4) | patch
hdl.{ast,dsl}, back.{pysim,rtlil}: allow multiple case values.
authorwhitequark <whitequark@whitequark.org>
Fri, 28 Jun 2019 04:37:08 +0000 (04:37 +0000)
committerwhitequark <whitequark@whitequark.org>
Fri, 28 Jun 2019 04:37:08 +0000 (04:37 +0000)
commit32446831b4a53784874702ebd737b15e8900505a
tree1297dd31415ae9a7693e893daa2abb335ebb156btree
parent48d4ee40313d94a90ce93911485c1a13556cdc17commit | diff
hdl.{ast,dsl}, back.{pysim,rtlil}: allow multiple case values.

This means that instead of:

    with m.Case(0b00):
        <body>
    with m.Case(0b01):
        <body>

it is legal to write:

    with m.Case(0b00, 0b01):
        <body>

with no change in semantics, and slightly nicer RTLIL or Verilog
output.

Fixes #103.
nmigen/back/pysim.py diff | blob | history
nmigen/back/rtlil.py diff | blob | history
nmigen/compat/fhdl/structure.py diff | blob | history
nmigen/hdl/ast.py diff | blob | history
nmigen/hdl/dsl.py diff | blob | history
nmigen/test/test_hdl_dsl.py diff | blob | history