Now timing reads work in single level of cache with simple cpu
authorRon Dreslinski <rdreslin@umich.edu>
Thu, 6 Jul 2006 19:15:37 +0000 (15:15 -0400)
committerRon Dreslinski <rdreslin@umich.edu>
Thu, 6 Jul 2006 19:15:37 +0000 (15:15 -0400)
commit329e32f8c63a5982b29c2d620e7d08708ec62fbd
tree9f77df5b3d07dfdcb309b98984c0c4dc3b4300df
parent4201ec84b2dd7d96148bf661124dd7b5d0e7204b
Now timing reads work in single level of cache with simple cpu

src/mem/cache/base_cache.cc:
src/mem/cache/base_cache.hh:
src/mem/cache/cache.hh:
    Changes to handle timing reads in Simple CPU (blocking buffers)

--HG--
extra : convert_revision : a2e7d4287d7cdfd1bbf9c929ecbeafde499a5b9f
src/mem/cache/base_cache.cc
src/mem/cache/base_cache.hh
src/mem/cache/cache.hh