git.libre-soc.org Git - gem5.git/commit

author	Gabe Black <gblack@eecs.umich.edu>
	Thu, 9 Jul 2009 06:02:20 +0000 (23:02 -0700)
committer	Gabe Black <gblack@eecs.umich.edu>
	Thu, 9 Jul 2009 06:02:20 +0000 (23:02 -0700)
commit	32daf6fc3fd34af0023ae74c2a1f8dd597f87242
tree	0868fb00a7546d90971bc18acd4f7b0bbce558c0	tree
parent	3e2cad8370d99f45ecf4d922d3ac8213e0d72644	commit \| diff

Registers: Add an ISA object which replaces the MiscRegFile.
This object encapsulates (or will eventually) the identity and characteristics
of the ISA in the CPU.

46 files changed:

src/arch/SConscript		diff \| blob \| history
src/arch/alpha/SConscript		diff \| blob \| history
src/arch/alpha/isa.cc	[new file with mode: 0644]	blob
src/arch/alpha/isa.hh	[new file with mode: 0644]	blob
src/arch/alpha/isa/main.isa		diff \| blob \| history
src/arch/alpha/regfile.cc		diff \| blob \| history
src/arch/alpha/regfile.hh		diff \| blob \| history
src/arch/arm/SConscript		diff \| blob \| history
src/arch/arm/isa.cc	[new file with mode: 0644]	blob
src/arch/arm/isa.hh	[new file with mode: 0644]	blob
src/arch/arm/regfile/misc_regfile.hh		diff \| blob \| history
src/arch/arm/regfile/regfile.cc		diff \| blob \| history
src/arch/arm/regfile/regfile.hh		diff \| blob \| history
src/arch/mips/SConscript		diff \| blob \| history
src/arch/mips/isa.cc	[new file with mode: 0644]	blob
src/arch/mips/isa.hh	[new file with mode: 0644]	blob
src/arch/mips/regfile.cc		diff \| blob \| history
src/arch/mips/regfile/regfile.cc		diff \| blob \| history
src/arch/mips/regfile/regfile.hh		diff \| blob \| history
src/arch/mips/utility.hh		diff \| blob \| history
src/arch/sparc/SConscript		diff \| blob \| history
src/arch/sparc/isa.cc	[new file with mode: 0644]	blob
src/arch/sparc/isa.hh	[new file with mode: 0644]	blob
src/arch/sparc/regfile.cc		diff \| blob \| history
src/arch/sparc/regfile.hh		diff \| blob \| history
src/arch/x86/SConscript		diff \| blob \| history
src/arch/x86/isa.cc	[new file with mode: 0644]	blob
src/arch/x86/isa.hh	[new file with mode: 0644]	blob
src/arch/x86/miscregfile.hh		diff \| blob \| history
src/arch/x86/process.cc		diff \| blob \| history
src/arch/x86/regfile.cc		diff \| blob \| history
src/arch/x86/regfile.hh		diff \| blob \| history
src/arch/x86/tlb.cc		diff \| blob \| history
src/arch/x86/utility.hh		diff \| blob \| history
src/cpu/inorder/cpu.cc		diff \| blob \| history
src/cpu/inorder/cpu.hh		diff \| blob \| history
src/cpu/inorder/thread_context.hh		diff \| blob \| history
src/cpu/o3/cpu.cc		diff \| blob \| history
src/cpu/o3/cpu.hh		diff \| blob \| history
src/cpu/o3/regfile.hh		diff \| blob \| history
src/cpu/o3/rename_impl.hh		diff \| blob \| history
src/cpu/o3/thread_context.hh		diff \| blob \| history
src/cpu/o3/thread_context_impl.hh		diff \| blob \| history
src/cpu/simple_thread.hh		diff \| blob \| history
src/cpu/thread_context.hh		diff \| blob \| history
src/kern/tru64/tru64.hh		diff \| blob \| history

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