misc: BaseCPU using ArchMMU instead of ArchDTB/ArchITB
authorGiacomo Travaglini <giacomo.travaglini@arm.com>
Fri, 13 Dec 2019 00:18:47 +0000 (00:18 +0000)
committerGiacomo Travaglini <giacomo.travaglini@arm.com>
Wed, 21 Oct 2020 09:33:39 +0000 (09:33 +0000)
commit330a5f7bad18764fe07eae79492d109112730128
tree8bb0f9fbc6306943b42075f76e77032190dd7c9b
parent85a36581d4c74f9d0edbaeb1f37516fe97b78274
misc: BaseCPU using ArchMMU instead of ArchDTB/ArchITB

With this commit we replace every TLB pointer stored in the
cpu model with a BaseMMU pointer.

JIRA: https://gem5.atlassian.net/browse/GEM5-790

Change-Id: I4932a32f68582b25cd252b5420b54d6a40ee15b8
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34976
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
48 files changed:
configs/common/Options.py
configs/common/cores/arm/HPI.py
configs/example/apu_se.py
configs/example/arm/devices.py
configs/example/fs.py
configs/example/se.py
configs/learning_gem5/part3/msi_caches.py
configs/learning_gem5/part3/ruby_caches_MI_example.py
src/arch/arm/ArmMMU.py
src/arch/arm/fastmodel/CortexA76/thread_context.cc
src/arch/arm/fastmodel/CortexA76/thread_context.hh
src/arch/arm/fastmodel/iris/Iris.py
src/arch/arm/fastmodel/iris/cpu.hh
src/arch/arm/fastmodel/iris/thread_context.cc
src/arch/arm/fastmodel/iris/thread_context.hh
src/arch/generic/BaseMMU.py
src/arch/riscv/RiscvMMU.py
src/arch/x86/X86MMU.py
src/cpu/BaseCPU.py
src/cpu/base.cc
src/cpu/base.hh
src/cpu/base_dyn_inst.hh
src/cpu/checker/cpu.cc
src/cpu/checker/cpu.hh
src/cpu/checker/cpu_impl.hh
src/cpu/checker/thread_context.hh
src/cpu/kvm/base.cc
src/cpu/minor/cpu.cc
src/cpu/minor/exec_context.hh
src/cpu/minor/fetch1.cc
src/cpu/minor/lsq.cc
src/cpu/o3/O3CPU.py
src/cpu/o3/cpu.cc
src/cpu/o3/cpu.hh
src/cpu/o3/fetch_impl.hh
src/cpu/o3/lsq_impl.hh
src/cpu/o3/lsq_unit.hh
src/cpu/o3/thread_context.hh
src/cpu/simple/BaseSimpleCPU.py
src/cpu/simple/atomic.cc
src/cpu/simple/base.cc
src/cpu/simple/exec_context.hh
src/cpu/simple/timing.cc
src/cpu/simple_thread.cc
src/cpu/simple_thread.hh
src/cpu/thread_context.hh
tests/configs/pc-simple-timing-ruby.py
tests/gem5/x86-boot-tests/system/caches.py