add variable bitwidth on read/write regs
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 25 Oct 2018 23:57:56 +0000 (00:57 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 25 Oct 2018 23:57:56 +0000 (00:57 +0100)
commit33188ae6d82c907b6bb6091143a9d45dac6659db
treed80675c847d6a3edda94d23278a9d35042144d15
parent89b13f56095c44eb7e2509c960f7dd9eb943b025
add variable bitwidth on read/write regs
riscv/insn_template_sv.cc
riscv/processor.cc
riscv/sv.cc
riscv/sv_insn_redirect.cc