vendor.xilinx_{spartan_3_6,7series}: reconsider default reset logic.

vendor.xilinx_{spartan_3_6,7series}: reconsider default reset logic.

On Xilinx devices, flip-flops are reset to their initial state with
an internal global reset network, but this network is deasserted
asynchronously to user clocks. Use BUFGCE and STARTUP to hold default
clock low until after GWE is deasserted.