RISC-V: Only relax to C.LUI when imm != 0 and rd != 0/2

RISC-V: Only relax to C.LUI when imm != 0 and rd != 0/2

This matches the ISA specification.  This also adds two tests: one to
make sure the assembler rejects invalid 'c.lui's, and one to make sure
we only relax valid 'c.lui's.

bfd/ChangeLog

2017-10-24  Andrew Waterman  <andrew@sifive.com>

        * elfnn-riscv.c (_bfd_riscv_relax_lui): Don't relax to c.lui
        when rd is x0.

include/ChangeLog

2017-10-24  Andrew Waterman  <andrew@sifive.com>

        * opcode/riscv.h (VALID_RVC_LUI_IMM): c.lui can't load the
        immediate 0.

gas/ChangeLog

2017-10-24  Andrew Waterman  <andrew@sifive.com>

        * testsuite/gas/riscv/c-lui-fail.d: New testcase.
        gas/testsuite/gas/riscv/c-lui-fail.l: Likewise.
        gas/testsuite/gas/riscv/c-lui-fail.s: Likewise.
        gas/testsuite/gas/riscv/riscv.exp: Likewise.

ld/ChangeLog

2017-10-24  Andrew Waterman  <andrew@sifive.com>

        * ld/testsuite/ld-riscv-elf/c-lui.d: New testcase.
        ld/testsuite/ld-riscv-elf/c-lui.s: Likewise.
        ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp: New test suite.