Re: [libre-riscv-dev] teaching the benefits of using nmigen over VHDL/Verilog
authorMichael Nolan <mtnolan2640@gmail.com>
Wed, 13 May 2020 18:51:48 +0000 (14:51 -0400)
committerlibre-riscv-dev <libre-riscv-dev@lists.libre-riscv.org>
Wed, 13 May 2020 18:51:53 +0000 (19:51 +0100)
commit3347a8a1ab813f10ae6ee5b0946aa393e5ba954e
tree9efb5cf24d0c1714bab6caef7167f943ae5ed7d3
parent13e0093621c3293191e967787620227cd6523cfa
Re: [libre-riscv-dev] teaching the benefits of using nmigen over VHDL/Verilog
f0/5e6ec9f6b879ebae403e05f4cc3941f9421ffd [new file with mode: 0644]