panfrost/midgard: Implement "pipeline register" prepass
authorAlyssa Rosenzweig <alyssa@rosenzweig.io>
Thu, 23 May 2019 01:40:23 +0000 (01:40 +0000)
committerAlyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tue, 4 Jun 2019 20:14:50 +0000 (20:14 +0000)
commit33800f461244435ed3256ed90fcba2271b387323
tree2cc90fa40d0946000535cc86a61feffacb20f748
parent2a79afc5f0a8500194cd6e60ff7ceb14c191c5c7
panfrost/midgard: Implement "pipeline register" prepass

This prepass, run after scheduling but before RA, specializes to
pipeline registers where possible. It walks the IR, checking whether
sources are ever used outside of the immediate bundle in which they are
written. If they are not, they are rewritten to a pipeline register (r24
or r25), valid only within the bundle itself. This has theoretical
benefits for power consumption and register pressure (and performance by
extension). While this is tested to work, it's not clear how much of a
win it really is, especially without an out-of-order scheduler (yet!).

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Ryan Houdek <Sonicadvance1@gmail.com>
src/gallium/drivers/panfrost/meson.build
src/gallium/drivers/panfrost/midgard/compiler.h
src/gallium/drivers/panfrost/midgard/midgard_ra_pipeline.c [new file with mode: 0644]
src/gallium/drivers/panfrost/midgard/midgard_schedule.c