slicc: added MOESI_CMP_directory, DMA SequencerMsg, parameterized controllers
authorDerek Hower <drh5@cs.wisc.edu>
Tue, 4 Aug 2009 17:52:52 +0000 (12:52 -0500)
committerDerek Hower <drh5@cs.wisc.edu>
Tue, 4 Aug 2009 17:52:52 +0000 (12:52 -0500)
commit33b28fde7aca9bf1ae16b9db09e71ccd44d3ae76
treefe2a4aee5517aed63f95e56ce4f085793826bdd4
parentc1e0bd1df4cf107bd543bcde9c9ab7be41d6dce3
slicc: added MOESI_CMP_directory, DMA SequencerMsg, parameterized controllers

This changeset contains a lot of different changes that are too
mingled to separate.  They are:

1.  Added MOESI_CMP_directory

I made the changes necessary to bring back MOESI_CMP_directory,
including adding a DMA controller.  I got rid of MOESI_CMP_directory_m
and made MOESI_CMP_directory use a memory controller. Added a new
configuration for two level protocols in general, and
MOESI_CMP_directory in particular.

2.  DMA Sequencer uses a generic SequencerMsg

I will eventually make the cache Sequencer use this type as well.  It
doesn't contain an offset field, just a physical address and a length.
MI_example has been updated to deal with this.

3. Parameterized Controllers

SLICC controllers can now take custom parameters to use for mapping,
latencies, etc.  Currently, only int parameters are supported.
47 files changed:
src/mem/gems_common/Map.hh
src/mem/protocol/MI_example-cache.sm
src/mem/protocol/MI_example-dir.sm
src/mem/protocol/MI_example-dma.sm
src/mem/protocol/MI_example-msg.sm
src/mem/protocol/MOESI_CMP_directory-L1cache.sm
src/mem/protocol/MOESI_CMP_directory-L2cache.sm
src/mem/protocol/MOESI_CMP_directory-dir.sm
src/mem/protocol/MOESI_CMP_directory-dma.sm [new file with mode: 0644]
src/mem/protocol/MOESI_CMP_directory-msg.sm
src/mem/protocol/MOESI_CMP_directory.slicc
src/mem/protocol/MOESI_CMP_directory_m-dir.sm [deleted file]
src/mem/protocol/MOESI_CMP_directory_m.slicc [deleted file]
src/mem/protocol/RubySlicc_ComponentMapping.sm
src/mem/protocol/RubySlicc_Exports.sm
src/mem/protocol/RubySlicc_Profiler.sm
src/mem/protocol/RubySlicc_Types.sm
src/mem/protocol/RubySlicc_Util.sm
src/mem/ruby/config/MI_example-homogeneous.rb
src/mem/ruby/config/MI_example.rb [new file with mode: 0644]
src/mem/ruby/config/MOESI_CMP_directory.rb [new file with mode: 0644]
src/mem/ruby/config/TwoLevel_SplitL1UnifiedL2.rb [new file with mode: 0644]
src/mem/ruby/config/cfg.rb
src/mem/ruby/config/defaults.rb
src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh
src/mem/ruby/slicc_interface/RubySlicc_Util.hh
src/mem/ruby/system/DMASequencer.cc
src/mem/ruby/system/DirectoryMemory.cc
src/mem/ruby/system/DirectoryMemory.hh
src/mem/ruby/system/PerfectCacheMemory.hh
src/mem/ruby/system/System.hh
src/mem/ruby/system/TimerTable.cc
src/mem/ruby/system/TimerTable.hh
src/mem/slicc/ast/AST.hh
src/mem/slicc/ast/ActionDeclAST.cc
src/mem/slicc/ast/ActionDeclAST.hh
src/mem/slicc/ast/EnqueueStatementAST.cc
src/mem/slicc/ast/FormalParamAST.cc
src/mem/slicc/ast/FormalParamAST.hh
src/mem/slicc/ast/FuncDeclAST.cc
src/mem/slicc/ast/FuncDeclAST.hh
src/mem/slicc/ast/MachineAST.cc
src/mem/slicc/ast/MachineAST.hh
src/mem/slicc/parser/parser.py
src/mem/slicc/parser/parser.yy
src/mem/slicc/symbols/StateMachine.cc
src/mem/slicc/symbols/StateMachine.hh