Fixed Verilog parser fix and more similar improvements
authorClifford Wolf <clifford@clifford.at>
Tue, 15 Mar 2016 11:22:31 +0000 (12:22 +0100)
committerClifford Wolf <clifford@clifford.at>
Tue, 15 Mar 2016 11:22:31 +0000 (12:22 +0100)
commit33c10350b22a8cc943cf3c294ee86969c5ce97f4
treec220eae5a94d444fc5d7fd74d190fd1ab47f8b51
parent81d4e9e7c1c311f837dadb1634c83b4e70929669
Fixed Verilog parser fix and more similar improvements
frontends/verilog/verilog_parser.y