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(parent: db5fd1e) | patch
back.rtlil: prepare for Yosys sigspec slicing improvements.
authorwhitequark <whitequark@whitequark.org>
Sun, 16 Dec 2018 18:03:14 +0000 (18:03 +0000)
committerwhitequark <whitequark@whitequark.org>
Sun, 16 Dec 2018 18:03:14 +0000 (18:03 +0000)
commit33f32a25f58f8562ccfb1de82118f576a5dcd71e
tree19bcef4863177aae012555806c712c660ef79958tree
parentdb5fd1e4c49e77dad65ca3dd0540a8d7da6deb8ecommit | diff
back.rtlil: prepare for Yosys sigspec slicing improvements.

See YosysHQ/yosys#741.
nmigen/back/rtlil.py diff | blob | history