xilinx: Fix srl regression.
authorMarcelina Kościelnicka <mwk@0x04.net>
Sun, 12 Jul 2020 15:54:07 +0000 (17:54 +0200)
committerMarcelina Kościelnicka <mwk@0x04.net>
Sun, 12 Jul 2020 21:41:27 +0000 (23:41 +0200)
commit347dd01c2f7dff6e8222c5f9d360f84a17c937b5
tree2ce79cc1ddda483a78510e7cfe717dc14bbd62ab
parentb33744b03ab8c8188e45656722d4a28c173ec67c
xilinx: Fix srl regression.

Of standard yosys cells, xilinx_srl only works on $_DFF_?_ and
$_DFFE_?P_, which get upgraded to $_SDFFE_?P?P_ by dfflegalize at the
point where xilinx_srl is called for non-abc9.  Fix this by running
ff_map.v first, resulting in FDRE cells, which are handled correctly.
techlibs/xilinx/synth_xilinx.cc
tests/arch/xilinx/nosrl.ys [new file with mode: 0644]