add Issue phase and writes/reads possible in CPU
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Tue, 2 May 2023 18:20:42 +0000 (19:20 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Tue, 2 May 2023 18:20:42 +0000 (19:20 +0100)
commit349a26b6c211922b2a322c6022494cc9830b28df
tree5bf7dfcc27ed187a8be44a71badbc16606e2b971
parent08752ee61ffc3e03a8fe7986cb551014dbbe91a9
add Issue phase and writes/reads possible in CPU
src/openpower/cyclemodel/inorder.py