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(parent: 2218ece) | patch
gen/build: use verilog 2001-style synthesis attributes for vivado (will need rework)
authorFlorent Kermarrec <florent@enjoy-digital.fr>
Thu, 11 Feb 2016 21:54:26 +0000 (22:54 +0100)
committerFlorent Kermarrec <florent@enjoy-digital.fr>
Thu, 11 Feb 2016 21:54:26 +0000 (22:54 +0100)
commit34b45e36184340e67f419eaa00c61d68c64de1fc
tree765c2ecf0010eb50d34a76914fbbbb41a36b1fb4tree
parent2218ece98a5344a024a3b7d42fcd040e3775903acommit | diff
gen/build: use verilog 2001-style synthesis attributes for vivado (will need rework)
litex/build/xilinx/common.py diff | blob | history
litex/gen/fhdl/structure.py diff | blob | history
litex/gen/fhdl/verilog.py diff | blob | history