Added SystemVerilog support for ++ and --
authorClifford Wolf <clifford@clifford.at>
Thu, 23 Feb 2017 10:21:33 +0000 (11:21 +0100)
committerClifford Wolf <clifford@clifford.at>
Thu, 23 Feb 2017 10:21:33 +0000 (11:21 +0100)
commit34d4e72132863279187950de259fb112ca749787
tree49f7148aaedd925ecc02570c0d28fdaedb04e3bf
parentd25b6a72ee2ffb68bb0cc1244e5b67dc4649f982
Added SystemVerilog support for ++ and --
frontends/verilog/verilog_lexer.l
frontends/verilog/verilog_parser.y