ARM: Decode to specialized conditional/unconditional versions of instructions.
authorGabe Black <gblack@eecs.umich.edu>
Wed, 2 Jun 2010 17:58:17 +0000 (12:58 -0500)
committerGabe Black <gblack@eecs.umich.edu>
Wed, 2 Jun 2010 17:58:17 +0000 (12:58 -0500)
commit358fdc2a40e8a455f508532b47e55f3252053805
tree4641a564de6d0ce42a372be77e35cde55e2c177c
parent596cbe19d4591b900acc022ff5a38fc7ee9a5df7
ARM: Decode to specialized conditional/unconditional versions of instructions.

This is to avoid condition code based dependences from effectively serializing
instructions when the instruction doesn't actually use them.
src/arch/arm/insts/pred_inst.hh
src/arch/arm/isa/formats/pred.isa
src/arch/arm/isa/insts/data.isa
src/arch/arm/isa/insts/macromem.isa
src/arch/arm/isa/insts/mem.isa
src/arch/arm/isa/insts/misc.isa
src/arch/arm/isa/insts/mult.isa
src/arch/arm/isa/operands.isa
src/arch/arm/isa/templates/pred.isa