Merge pull request #210 from DurandA/master
authorTim Ansell <me@mith.ro>
Thu, 4 Jul 2019 00:23:36 +0000 (17:23 -0700)
committerGitHub <noreply@github.com>
Thu, 4 Jul 2019 00:23:36 +0000 (17:23 -0700)
commit359b8fe4bbda113289a334dcf296eb8856215f2d
treeb3bae92bb479a9df7470af0633179a63bb18f971
parent4ee9c53f185ac6dd9c4aa69a7547e9bc037acc25
parent68eeba918186f5bd3d3f4e0552b286f7db08d5a3
Merge pull request #210 from DurandA/master

Add verilog submodule from CPU cores to manifest