soc/cores/clock: reset PLL/MMCM on all 7-series/Ultrascale with self.reset signal
authorFlorent Kermarrec <florent@enjoy-digital.fr>
Wed, 20 Nov 2019 18:24:40 +0000 (19:24 +0100)
committerFlorent Kermarrec <florent@enjoy-digital.fr>
Wed, 20 Nov 2019 18:24:40 +0000 (19:24 +0100)
commit36107cdfd79752289b24fb6200a90094d78ad597
treef2fed49cb95d4f4b8e042cbe6a586a4342206ee3
parente8e70b164ae5e8f324c207a14873bfcc2350c3d9
soc/cores/clock: reset PLL/MMCM on all 7-series/Ultrascale with self.reset signal
litex/soc/cores/clock.py