Added support for non-const === and !== (for miter circuits)
authorClifford Wolf <clifford@clifford.at>
Fri, 27 Dec 2013 13:20:15 +0000 (14:20 +0100)
committerClifford Wolf <clifford@clifford.at>
Fri, 27 Dec 2013 13:20:15 +0000 (14:20 +0100)
commit369bf81a7049c96f62af084bb5007fbf45e36ab4
tree92071580c9bd60888ee5861d59457947a8adfde7
parentecc30255ba70910777a4586f5bd6abc818073293
Added support for non-const === and !== (for miter circuits)
backends/verilog/verilog_backend.cc
frontends/ast/genrtlil.cc
kernel/celltypes.h
kernel/rtlil.cc
kernel/satgen.h
passes/extract/extract.cc
passes/opt/opt_const.cc
passes/proc/proc_arst.cc
techlibs/common/simlib.v
techlibs/common/stdcells.v