liteeth/example_designs: add false path between clock domains (speed up implementatio...
authorFlorent Kermarrec <florent@enjoy-digital.fr>
Mon, 22 Jun 2015 22:37:31 +0000 (00:37 +0200)
committerFlorent Kermarrec <florent@enjoy-digital.fr>
Mon, 22 Jun 2015 23:08:49 +0000 (01:08 +0200)
commit369cf4c4d7694d33141f9b706d50dcf94cbc5363
tree8ffb506f0c997777dc7a0fb88f56a34693faa072
parent5c939b85efa45e9c4158b39f958ff6f7059fe4db
liteeth/example_designs: add false path between clock domains (speed up implementation) and use automatic PHY detection
misoclib/com/liteeth/example_designs/targets/base.py