arch, mem, sim: Consolidate and rename the SE mode page table classes.
authorGabe Black <gabeblack@google.com>
Thu, 4 Jan 2018 09:22:49 +0000 (01:22 -0800)
committerGabe Black <gabeblack@google.com>
Fri, 19 Jan 2018 20:20:57 +0000 (20:20 +0000)
commit372adea6879ac549df4a415b5913d28b6683d535
tree2319ce7ae4f5cbdd381038cea4f7f9ce33d3c835
parentd76798c3e5611a9673bd1da9589a0081610cef5b
arch, mem, sim: Consolidate and rename the SE mode page table classes.

Now that Nothing inherits from PageTableBase directly, it can be
merged into FuncPageTable. This change also takes the opportunity to
rename the combined class to EmulationPageTable which lets you know
that it's specifically for SE mode.

Also remove the page table entry cache since it doesn't seem to
actually improve performance. The TLBs likely absorb the majority of
the locality, essentially acting like a cache like they would in real
hardware.

Change-Id: If1bcb91aed08686603bf7bee37298c0eee826e13
Reviewed-on: https://gem5-review.googlesource.com/7342
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
14 files changed:
src/arch/alpha/process.cc
src/arch/arm/process.cc
src/arch/mips/process.cc
src/arch/power/process.cc
src/arch/riscv/process.cc
src/arch/sparc/process.cc
src/arch/x86/process.cc
src/mem/multi_level_page_table.hh
src/mem/multi_level_page_table_impl.hh
src/mem/page_table.cc
src/mem/page_table.hh
src/mem/se_translating_port_proxy.hh
src/sim/process.cc
src/sim/process.hh