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(parent: eb20195) | patch
dmi_dtm_ecp5: Use ECP5 JTAGG for DMI
authorMatt Johnston <matt@codeconstruct.com.au>
Fri, 26 Nov 2021 02:47:07 +0000 (10:47 +0800)
committerMatt Johnston <matt@codeconstruct.com.au>
Fri, 4 Feb 2022 08:09:28 +0000 (16:09 +0800)
commit3775650df3a53264f37dcd14223248da7c9d9381
tree0fa6b1d3dda99462e97a89b4d4f30c78b093dafdtree
parenteb20195a101af2e699a025b6fd5d656612c75a1ecommit | diff
dmi_dtm_ecp5: Use ECP5 JTAGG for DMI

This uses the JTAGG primitive which is similar to BSCANE2.
The LUT4 delay approach came from Florian and Greg in
https://github.com/enjoy-digital/litex/pull/1087

Has been tested on an OrangeCrab with 48MHz sysclk
FT232H up to 30MHz (though libusb/urjtag is by far the bottleneck vs
the JTAG clock)

Signed-off-by: Matt Johnston <matt@codeconstruct.com.au>
Makefile diff | blob | history
dmi_dtm_ecp5.vhdl [new file with mode: 0644] blob