o Make tic80 insn file more `cache ready'
authorAndrew Cagney <cagney@redhat.com>
Fri, 16 May 1997 03:27:40 +0000 (03:27 +0000)
committerAndrew Cagney <cagney@redhat.com>
Fri, 16 May 1997 03:27:40 +0000 (03:27 +0000)
commit37a684b84d5c722848ebdc7203052d65c6b35e30
tree3d7fa5b15efab746e9b8cc87449fa8664b6ed359
parent77bd8dfa1f3678ea3c3d05f40de29a36802d21f5
o Make tic80 insn file more `cache ready'
o Have igen always zero r0 instead of constantly checking if
the designated register is r0.
sim/igen/ChangeLog
sim/igen/gen-semantics.c
sim/tic80/ChangeLog
sim/tic80/Makefile.in
sim/tic80/cpu.h
sim/tic80/ic
sim/tic80/insns
sim/tic80/interp.c
sim/tic80/sim-calls.c