projects / riscv-isa-sim.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 19d2ee7) | patch
big reorganisation to support twin-predication
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 4 Oct 2018 09:16:10 +0000 (10:16 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 4 Oct 2018 09:16:10 +0000 (10:16 +0100)
commit37a9762f8bd82f66397ba1cfa1215660247b1e66
tree0460f98fa0830ddfec3a78536e4c1b4f91f412dftree
parent19d2ee777216e78024a2215c38b9a09ac1ccde88commit | diff
big reorganisation to support twin-predication

twin predication is on certain operations like LOAD, STORE, C.MV, FCVT
where the effect is similar to VSPLAT, VINSERT, and also bitmanip
scatter/gather.
id_regs.py diff | blob | history
riscv/insn_template_sv.cc diff | blob | history
riscv/sv.cc diff | blob | history
riscv/sv_decode.h diff | blob | history
Simple-V augmented version of spike