RISC-V: Fix requirement handling on Zhinx+{D,Q}

RISC-V: Fix requirement handling on Zhinx+{D,Q}

This commit fixes how instructions are masked on Zhinx+Z{d,q}inx.
fcvt.h.d and fcvt.d.h require ((D&&Zfh)||(Zdinx&&Zhinx)) and
fcvt.h.q and fcvt.q.h require ((Q&&Zfh)||(Zqinx&&Zhinx)).

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_multi_subset_supports): Fix feature gate
	on INSN_CLASS_{D,Q}_AND_ZFH_INX.
	(riscv_multi_subset_supports_ext): Fix feature gate diagnostics
	on INSN_CLASS_{D,Q}_AND_ZFH_INX.

gas/ChangeLog:

	* testsuite/gas/riscv/fp-zhinx-insns.d: Add Zqinx to -march
	for proper testing.