projects / riscv-isa-sim.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: d34ff3b) | patch
adding sv vector length CSR to processor state, and csr get/set
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 27 Sep 2018 13:24:48 +0000 (14:24 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 27 Sep 2018 13:24:48 +0000 (14:24 +0100)
commit384b42e2bb5a8a0477e7abca8e46124f7e34a422
treeb715c3d7ded800e43216cf91b4a75d354b4e7b20tree
parentd34ff3b34a62e75bd991b987ccb8634a4605a982commit | diff
adding sv vector length CSR to processor state, and csr get/set

32 CSRs are used up, here, as SETVL requires not only an immediate
but also a target integer register in which the SETVL value is
stored.
riscv/encoding.h diff | blob | history
riscv/processor.cc diff | blob | history
riscv/processor.h diff | blob | history
Simple-V augmented version of spike