HDL_workflow/ECP5_FPGA provide two images showing different orientation
authorCole Poirier <colepoirier@gmail.com>
Wed, 4 Nov 2020 01:09:32 +0000 (17:09 -0800)
committerCole Poirier <colepoirier@gmail.com>
Wed, 4 Nov 2020 01:10:25 +0000 (17:10 -0800)
commit38c5b6f9e3eb20838650232d8f681985e9e9128d
treedff9534df79ff8d64e8d6b25bd09b8daffa55b5e
parent9d97e7babb3d2e49ec8f11be8b93d57753b535f8
HDL_workflow/ECP5_FPGA provide two images showing different orientation
of stlinkv2
HDL_workflow/jtag_wires_ulx3s_stlinkv2.jpg [deleted file]
HDL_workflow/jtag_wires_ulx3s_stlinkv2_opposite_orientation_to_jtag.jpg [new file with mode: 0644]
HDL_workflow/jtag_wires_ulx3s_stlinkv2_same_orientation_as_jtag.jpg [new file with mode: 0644]