RISC-V: Reorganize and enhance 'Zfinx' tests

RISC-V: Reorganize and enhance 'Zfinx' tests

This commit adds certain test cases for 'Zfinx'/'Zdinx'/'Zqinx' extensions
and reorganizes them, fixing coding style while improving coverage.
This is partially based on jiawei's 'Zhinx' testcases.

gas/ChangeLog:

	* testsuite/gas/riscv/zfinx.s: Use different registers for
	better encode space testing.  Make indentation consistent.
	Add tests for instruction with rounding mode.  Change march
	to minimum required extensions.  Remove source line.
	* testsuite/gas/riscv/zfinx.d: Likewise.
	* testsuite/gas/riscv/zdinx.s: Likewise.
	* testsuite/gas/riscv/zdinx.d: Likewise.
	* testsuite/gas/riscv/zqinx.s: Likewise.
	Also use even-numbered registers to use valid register pairs.
	* testsuite/gas/riscv/zqinx.d: Likewise.

Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
Signed-off-by: jiawei <jiawei@iscas.ac.cn>