projects / yosys.git / commit
| author | Clifford Wolf <clifford@clifford.at> | |
| Wed, 7 Jan 2015 23:05:11 +0000 (00:05 +0100) | ||
| committer | Clifford Wolf <clifford@clifford.at> | |
| Wed, 7 Jan 2015 23:05:11 +0000 (00:05 +0100) | ||
| commit | 38dfc5c580c8ba418783ec8cbee1a78c7cd5f788 | |
| tree | 9683e27d3fbfee52ed01570bda8a7f2f1ed7fbee | tree |
| parent | fd787609aad5fcd7a817c4a7da0f6d89894c551a | commit | diff |
| techlibs/xilinx/cells_sim.v | [new file with mode: 0644] | blob |