arch-riscv: Fix disassembling for fence and fence.i
authorIan Jiang <ianjiang.ict@gmail.com>
Thu, 14 Nov 2019 08:41:25 +0000 (16:41 +0800)
committerIan Jiang <ianjiang.ict@gmail.com>
Tue, 26 Nov 2019 03:38:22 +0000 (03:38 +0000)
commit390f7b917757887674ab441979f36bffeedb646a
treeb9c6e3a4d7201bd08b871cbf247fa53576cbf9c8
parent57e951f6eae1de88988a9b13035c07985a0bcd73
arch-riscv: Fix disassembling for fence and fence.i

The original Gem5 does not give correct disassembly for instruction fence
and fence.i. This patch fixes the problem by adding two bitfields PRED and
SUCC and a new format FenceOp and a template FenceExecute, in which
operands are generated based on PRED and SUCC in the disassembling
function.

Change-Id: I78dbf125fef86ce40785c498a318ffb1569da46c
Signed-off-by: Ian Jiang <ianjiang.ict@gmail.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22569
Reviewed-by: Alec Roelke <alec.roelke@gmail.com>
Maintainer: Alec Roelke <alec.roelke@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
src/arch/riscv/isa/bitfields.isa
src/arch/riscv/isa/decoder.isa
src/arch/riscv/isa/formats/standard.isa