mem: Fix DRAM controller to operate on its own address space
authorNikos Nikoleris <nikos.nikoleris@arm.com>
Thu, 12 Sep 2019 15:10:26 +0000 (16:10 +0100)
committerNikos Nikoleris <nikos.nikoleris@arm.com>
Tue, 29 Oct 2019 09:48:10 +0000 (09:48 +0000)
commit39220ef3681deb8c224cdcf28efdaa74bfa2facd
tree58552932697f996b2a30ab336a862dd03b9a4619
parent12cf816745fa9fe2718e54d19b33f303b15b90aa
mem: Fix DRAM controller to operate on its own address space

Typically, a memory controller is assigned an address range of the
form [start, end). This address range might be interleaved and
therefore only a non-continuous subset of the addresses in the address
range is handed by this controller.

Prior to this patch, the DRAM controller was unaware of the
interleaving and as a result the address range could affect the
mapping of addresses to DRAM ranks, rows and columns. This patch
changes the DRAM controller, to transform the input address to a
continuous range of the form [0, size). As a result the DRAM
controller always operates on a dense and continuous address range
regardlesss of the system configuration.

Change-Id: I7d273a630928421d1854658c9bb0ab34e9360851
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19328
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Wendy Elsasser <wendy.elsasser@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
configs/common/MemConfig.py
src/mem/DRAMCtrl.py
src/mem/dram_ctrl.cc
src/mem/dram_ctrl.hh